Edma Clear Error Register (Edma_Cerr) - Freescale Semiconductor MCF52277 Reference Manual

Field
5–4 Reserved, must be cleared.
3–0 Clear interrupt request. Clears the corresponding bit in EDMA_INT.
CINT

17.6.10 eDMA Clear Error Register (EDMA_CERR)

The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERR
to disable the error condition flag for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_ERR to be cleared. Setting the CAEI bit provides a global clear function,
forcing the EDMA_ERR contents to be cleared, clearing all channel error indicators. Reads of this register
return all zeroes.
Address: 0xFC04_401D (EDMA_CERR)
7
R 0
W
Reset 0
Field
7 Reserved, must be cleared.
6 Clear all error indicators.
CAEI 0 Clear only those EDMA_ERR bits specified in the CERR field.
1 Clear all bits in EDMA_ERR.
5–4 Reserved, must be cleared.
3–0 Clear error indicator. Clears the corresponding bit in EDMA_ERR.
CERR
17.6.11 eDMA Set START Bit Register (EDMA_SSRT)
The EDMA_SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the
given channel. The data value on a register write causes the START bit in the corresponding transfer
control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to
be set. Reads of this register return all zeroes.
Freescale Semiconductor
Table 17-12. EDMA_CINT Field Descriptions (continued)
6 5
0 0
CAEI
0 0
Figure 17-12. eDMA Clear Error Register (EDMA_CERR)
Table 17-13. EDMA_CERR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Description
4 3
0 0
0 0
Description
Enhanced Direct Memory Access (eDMA)
Access: User write-only
2 1
0 0
CERR
0 0
0
0
0
17-13