Freescale Semiconductor MCF52277 Reference Manual page 779

15
Command
Result
Table 32-23 shows the definition of DRc encoding.
DRc[4:0]
0x00
0x01–0x1F
Command Sequence:
Operand Data:
Result Data:
32.5.3.3.15 Write Debug Module Register (
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
Freescale Semiconductor
14 13 12 11 10
0x2
Figure 32-40.
RDMREG
Table 32-23. Definition of DRc Encoding—Read
Debug Register Definition
Configuration/Status
Reserved
RDMREG
???
Figure 32-41.
None
The contents of the selected debug register are returned as a longword value. The
data is returned most-significant word first.
MCF52277 Reference Manual, Rev. 1
9 8 7 6
0xD 100
D[31:16]
D[15:0]
Command/Result Formats
Mnemonic
CSR
—
XXX NEXT CMD
MS RESULT LS RESULT
XXX NEXT CMD
'ILLEGAL' 'NOT READY'
Command Sequence
RDMREG
)
WDMREG
5 4 3 2 1
DRc
Initial State Page
0x0090_0000 p. 32-7
—
Debug Module
0
—
32-39