Block Diagram - Freescale Semiconductor MCF52277 Reference Manual

SDRAM Controller (SDRAMC)
19.1.1

Block Diagram

Block diagram of the SDRAM controller:
19.1.2 Features
The SDRAM controller contains:
• Supports standard SDRAM (single data rate, or SDR) and dual data rate (DDR) SDRAM; one or
the other, not mixed.
• Support for lower-power/mobile DDR SDRAM.
• Dynamic 16- or 32-bit fixed memory data port width.
• 16 bytes critical word first burst transfer. Supports sequential address order only.
• Up to 14 lines of row address, up to 12 (in 32-bit bus mode) or 13 (in 16-bit bus mode) column
address lines, 2 bits of bank address, and two pinned-out chip selects. The maximum row bits plus
column bits equals 24 in 32-bit bus mode or 25 in 16-bit bus mode.
• Minimum memory configuration of 8 MByte
— 11 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA), 32-bit bus,
one chip select
19-2
Column
Address
ADDR
Bank
Input
MUX
Row
IPS Interface Register
File
Address
Controls
Data in [63:0]
Data out [63:0]
Figure 19-1. SDRAM Controller Block Diagram
MCF52277 Reference Manual, Rev. 1
Column
Address Address
Bank
Pipeline Output
Row
Latches MUX
Command
Type
SDRAM
Controller
State
Machine
Write Data
Buffer
Read Data
Buffer
SD_A[13:0]
SD_BA[1:0]
SD_CLK/CLK
SD_CKE
SD_CS[1:0]
SD_RAS
SD_CAS
SD_WE
SD_SDRDQS
SD_DQS[3:2]
SD_DQM[3:0]
SD_D[31:0]
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