Panning - Freescale Semiconductor MCF52277 Reference Manual

21.4.3

Panning

Panning offset (POS) is expressed in bits, not pixels, so when operating in any mode other than 1 bpp, only
even pixel boundaries are valid. In 12 bpp mode, the pixels are aligned to 16-bit boundaries, and POS also
must align to these boundaries.
SSA and POS are located in isolated registers and are double buffered because they are dynamic
parameters likely to change while the LCDC is running. New values of SSA and POS do not take effect
until the beginning of the next frame. A typical panning algorithm includes an interrupt at the beginning
of the frame. In the interrupt service routine, POS and/or SSA are updated (the old values are internally
latched). The updates take effect on the next frame.
21.4.4 Display Data Mapping
The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16/18 bpp in color mode. System memory
data mapping in 2/4/8/12/16/18 bpp modes is shown in
In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, to leave
4 bits unused. In 18 bpp mode, 32 bits of memory are used for each pixel,
leaving 14 bits unused. Refer to
Freescale Semiconductor
NOTE
Figure 21-30
P0 P1 P2 P3
LCD Screen
Figure 21-29. Pixel Location on Display Screen
MCF52277 Reference Manual, Rev. 1
Liquid Crystal Display Controller (LCDC)
Figure 21-29.
and Figure 21-31.
21-31