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DMA Serial Peripheral Interface (DSPI)
29.4.4.4
Modified SPI Transfer Format (MTFE = 1, CPHA = 1)
Figure 29-17
shows the modified transfer format for CPHA is set. Only the condition where CPOL is
cleared is described. At the start of a transfer, the DSPI asserts the DSPI_PCSn signal to the slave device.
After the PCS to SCK delay has elapsed the master and the slave put data on their DSPI_SOUT pins at the
first edge of DSPI_SCK. The slave samples the master DSPI_SOUT signal on the even numbered edges
of DSPI_SCK. The master samples the slave DSPI_SOUT signal on the odd numbered DSPI_SCK edges
starting with the third DSPI_SCK edge. The slave samples the last bit on the last edge of the DSPI_SCK.
The master samples the last slave DSPI_SOUT bit one half DSPI_SCK cycle after the last edge of
DSPI_SCK. No clock edge is visible on the master DSPI_SCK pin during the sampling of the last bit. The
SCK to PCS delay must be greater or equal to half of the DSPI_SCK period.
For correct operation of the modified transfer format, the user must
thoroughly analyze the SPI link timing budget.
System Clock
DSPI_SCK
Slave Sample
Master Sample
Master DSPI_SOUT
Slave DSPI_SOUT
DSPI_PCSn
Figure 29-17. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, Fsck = Fsys/4)
29.4.4.5
Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must remain selected
between several sequential serial transfers. The continuous selection format provides the flexibility to
handle both cases. The continuous selection format is enabled for the SPI configuration by setting the
DSPI_PUSHR[CONT] bit.
When CONT is cleared, DSPI drives the asserted chip select signals to their idle states in between frames.
The idle states of the chip select signals are selected by the DSPI_MCR[PCSIS] field.
the timing diagram for two four-bit transfers with CPHA set and CONT cleared.
29-30
1
2
3
t
CSC
t
= PCS to SCK delay.
CSC
t
= After SCK delay.
ASC
MCF52277 Reference Manual, Rev. 1
NOTE
4
5
6
t
ASC
Figure 29-18
shows
Freescale Semiconductor
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