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IEEE 1149.1 Test Access Port (JTAG)
33.5
Initialization/Application Information
33.5.1
Restrictions
The test logic is a static logic design, and TCLK can be stopped in a high or low state without loss of data.
However, the system clock is not synchronized to TCLK internally. Any mixed operation using the test
logic and system functional logic requires external synchronization.
Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive
configurations in which MCU output drivers are enabled into actively driven networks.
Low-power stop mode considerations:
•
The TAP controller must be in the test-logic-reset state to enter or remain in the low-power stop
mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not
otherwise affect device functionality.
•
The TCLK input is not blocked in low-power stop mode. To consume minimal power, the TCLK
input should be externally connected to EV
•
The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power consumption
in low-power stop mode, these three pins should be connected to EV
33.5.2
Nonscan Chain Operation
Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent
to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be
connected to ground. However, because there is a pull-up on TRST, some amount of current results. The
internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without
asserting TRST.
33-10
.
DD
MCF52277 Reference Manual, Rev. 1
or left unconnected.
DD
Freescale Semiconductor
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