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DMA Serial Peripheral Interface (DSPI)
Table 29-16
shows an example of the computed delay after transfer.
PDT
01
29.4.4
Transfer Formats
The serial communications clock (DSPI_SCK) signal and the DSPI_PCSn signals control the SPI serial
communication. The DSPI_SCK signal provided by the master device synchronizes shifting and sampling
of the data by the DSPI_SIN and DSPI_SOUT pins. The DSPI_PCSn signals serve as enable signals for
the slave devices.
When the DSPI is the bus master, the DSPI_CTARn[CPOL, CPHA] bits select the polarity and phase of
the DSPI_SCK signal. The polarity bit selects the idle state of the DSPI_SCK. The clock phase bit selects
if the data on DSPI_SOUT is valid before or on the first DSPI_SCK edge.
When the DSPI is the bus slave, the DSPI_CTAR0[CPOL, CPHA] bits select the polarity and phase of the
serial clock. Even though the bus slave does not control the DSPI_SCK signal, clock polarity, clock phase,
and number of bits to transfer must be identical for the master device and the slave device to ensure proper
transmission.
The DSPI supports four different transfer formats:
•
Classic SPI with CPHA = 0
•
Classic SPI with CPHA = 1
•
Modified transfer format with CPHA = 0
•
Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The DSPI_MCR[MTFE] bit selects between classic SPI format and
modified transfer format. The classic SPI formats are described in
Format (CPHA =
0)" and
transfer formats are described in
0)"
and
Section 29.4.4.4, "Modified SPI Transfer Format (MTFE = 1, CPHA = 1)."
29.4.4.1
Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in
data bit is available on the first clock edge. In this format, the master and slave sample their DSPI_SIN
pins on the odd-numbered DSPI_SCK edges and change the data on their DSPI_SOUT pins on the
even-numbered DSPI_SCK edges.
29-26
Table 29-16. Delay after Transfer Computation Example
Prescaler
DT
Value
3
1110
Section 29.4.4.2, "Classic SPI Transfer Format (CPHA = 1)."
Section 29.4.4.3, "Modified SPI Transfer Format (MTFE = 1, CPHA =
Figure 29-14
communicates with peripheral SPI slave devices where the first
MCF52277 Reference Manual, Rev. 1
Scaler
f
Delay after Transfer
SYS/2
Value
32768
100 MHz
Section 29.4.4.1, "Classic SPI Transfer
0.98 ms
The modified
Freescale Semiconductor
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