Features - Freescale Semiconductor MCF52277 Reference Manual

IEEE 1149.1 Test Access Port (JTAG)
33.1.2

Features

The basic features of the JTAG module are the following:
• Performs boundary-scan operations to test circuit board electrical continuity
• Bypasses instruction to reduce the shift register path to a single cell
• Sets chip output pins to safety states while executing the bypass instruction
• Samples the system pins during operation and transparently shifts out the result
• Selects between JTAG TAP controller and Background Debug Module (BDM) using a dedicated
JTAG_EN pin
33.1.3 Modes of Operation
The JTAG_EN pin can select between the following modes of operation:
• JTAG mode (JTAG_EN = 1)
• Background debug mode (BDM)—for more information, refer to
Debug Mode (BDM)"; (JTAG_EN = 0).
33.2 External Signal Description
The JTAG module has five input and one output external signals, as described in
Name Direction
JTAG_EN Input
TCLK Input
TMS/BKPT Input
TDI/DSI Input
TRST/DSCLK Input
TDO/DSO Output
33.2.1 JTAG Enable (JTAG_EN)
The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is
selected; if it is high, the JTAG is selected.
JTAG_EN logic state.
33-2
Table 33-1. Signal Properties
Function
JTAG/BDM selector input
JTAG Test clock input
JTAG Test mode select / BDM Breakpoint
JTAG Test data input / BDM Development serial input
JTAG Test reset input / BDM Development serial clock
JTAG Test data output / BDM Development serial output
Table 33-2
MCF52277 Reference Manual, Rev. 1
Section 32.5, "Background
summarizes the pin function selected depending on
Table 33-1.
Reset State Pull up
— —
— Active
— Active
— Active
— Active
Hi-Z / 0 —
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