Table of Contents
Advertisement
Chapter 15
Interrupt Controller Modules
15.1
Introduction
This section details the functionality of the interrupt controllers (INTC0, INTC1). The general features of
the interrupt controller block include:
•
128 fully-programmable interrupt sources. Not all possible interrupt source locations are used on
this device.
•
Each of the sources has a unique interrupt control register (ICR0n, ICR1n) to define the
software-assigned levels.
•
Unique vector number for each interrupt source.
•
Ability to mask any individual interrupt source, plus global mask-all capability.
•
Supports hardware and software interrupt acknowledge cycles.
•
Wake-up signal from low-power stop modes.
The 64, fully-programmable interrupt sources for the two interrupt controllers manage the complete set of
interrupt sources from all of the modules on the device. This section describes how the interrupt sources
are mapped to the interrupt controller logic and how interrupts are serviced.
15.1.1
68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the interrupt controllers, a brief review of the interrupt architecture
of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once-per-instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine's status register (SR). If
the priority level is greater than the SR[I] field at the sample point, the processor suspends normal
instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as
non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and
may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire device
requires that, after asserted, the interrupt source remain asserted until explicitly disabled by the interrupt
service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address
Freescale Semiconductor
MCF52277 Reference Manual, Rev. 1
15-1
Advertisement
Table of Contents
