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Field
31–26
Vertical sync pulse width. Specifies the width, in lines, of the LCD_VSYNC pulse for active mode (TFT=1). For a
V_WIDTH
value of 0x01, the vertical sync pulse encompasses one LCD_HSYNC pulse. For a value of 0x02, the vertical sync
pulse encompasses two LCD_HSYNC pulses, and so on. For passive mode (TFT=0) and non-color mode, see
Figure
21-39.
25–16
Reserved, must be cleared.
15–8
Wait between frames 1. Defines the delay, in lines, between the end of the LCD_OE pulse and the beginning of
V_WAIT_1
the LCD_VSYNC pulse for active mode (TFT=1). This field has no meaning in passive non-color mode. The actual
delay is V_WAIT_1 lines. In passive color mode, this field is the delay, measured in virtual clock periods, between
the last line of the frame to the beginning of the next frame.
7–0
Wait between frames 2. Defines the delay, in lines, between the end of the LCD_VSYNC pulse and the beginning
V_WAIT_2
of the LCD_OE pulse of the first line in active mode (TFT=1). The actual delay is V_WAIT_2 lines. Set this field to
zero for passive non-color mode. The minimum value of this field is 0x01.
21.3.10 LCDC Panning Offset Register (LCD_POR)
The panning offset register sets up the panning for the image.
Address: 0xFC0A_C024 (LCD_POR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
Table 21-12. LCD_VCR Field Descriptions
Figure 21-11. LCD Panning Offset Register (LCD_POR)
MCF52277 Reference Manual, Rev. 1
Liquid Crystal Display Controller (LCDC)
Description
Access: User read/write
8
7
6
5
4
3
2
1
0
POS
21-13
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