Freescale Semiconductor MCF52277 Reference Manual page 58

Signal Descriptions
Signal Name
Breakpoint
Development Serial
Input
Development Serial
Output
Processor Status Clock PSTCLK
Debug Data
Processor Status
Outputs
All Processor Status
Outputs
PST[3:0]
(MCF52274)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
2-14
Table 2-21. Debug Support Signals (continued)
Abbreviation
BKPT Used to request a manual breakpoint.
DSI Internally-synchronized signal provides data input for the serial
communication port to the BDM module.
DSO Internally-registered signal provides serial output communication for
BDM module responses.
Used by the development system to know when to sample DDATA and
PST signals.
DDATA[3:0] Display captured processor data and breakpoint status. The PSTCLK
signal can be used by the development system to know when to
sample DDATA[3:0].
Only present on the BGA device (MCF52277).
PST[3:0] Indicate core status, as shown in
synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
Only present on the BGA device (MCF52277).
ALLPST ALLPST is a logical AND of the four PST signals and is present in
place of PST[3:0] and DDATA[3:0] on the LQFP device (MCF52274).
When asserted, reflects that the core is halted.
Table 2-22. Processor Status
ALLPST
(MCF52277)
0 Continue execution
0 Begin execution of one instruction
0 Reserved
0 Entry into user mode
0 Begin execution of PULSE and WDDATA instructions
0 Begin execution of taken branch
0 Reserved
0 Begin execution of RTE instruction
0 Begin one-byte transfer on DDATA
0 Begin two-byte transfer on DDATA
0 Begin three-byte transfer on DDATA
0 Begin four-byte transfer on DDATA
0 Exception processing
0 Reserved
MCF52277 Reference Manual, Rev. 1
Function
Table 2-22. Debug mode timing is
Processor Status
I/O
I
I
O
O
O
O
O
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