Freescale Semiconductor MCF52277 Reference Manual page 610

Synchronous Serial Interface (SSI)
• Rx frame sync initiated one bit before data is received (SSI_RCR[REFS] = 1)
• Tx shifting w.r.t. bit 0 of TXSR (SSI_TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (SSI_RCR[RXBIT0] = 1)
• Tx FIFO is enabled (SSI_TCR[TFEN0] = 1)
• Rx FIFO is enabled (SSI_RCR[RFEN0] = 1)
• Internally-generated frame sync (SSI_TCR[TFDIR] = 1)
• Externally-generated bit clock (SSI_TCR[TXDIR] = 0)
Any alteration of these bits does not affect the operational conditions of the SSI unless AC97 mode is
deselected. Hence, the only control bits that need to be set to configure the data transmission/reception are
the SSI_CCR[WL, DC] bits. In AC97 mode, the WL bits can only legally take the values corresponding
to 16-bit (truncated data) or 20-bit time slots. If the WL bits are set to select 16-bit time slots, while
receiving, the SSI pads the data (four least significant bits) with 0s, and while receiving, the SSI stores only
the 16 most significant bits in the Rx FIFO.
The following sequence should be followed for programming the SSI to work in AC97 mode:
1. Program the SSI_CCR[WL] bits to a value corresponding to 16 or 20 bits. The WL bit setting is
only for the data portion of the AC97 frame (slots #3 through #12). The tag slot (slot #0) is always
16-bits wide and the command address and command data slots (slots #1 and #2) are always 20 bits
wide.
2. Select the number of time slots through the SSI_CCR[DC] bits. For AC97 operation, the DC bits
should be set to a value of 0xC, resulting in 13 time slots per frame.
3. Write data to be transmitted in Tx FIFO 0 (through Tx data register 0)
4. Program the SSI_ACR[FV, TIF, RD, WR and FRDIV] bits
5. Update the contents of SSI_ACADD, SSI_ACDAT and SSI_ATAG (for fixed mode only)
registers
6. Enable AC97 mode (SSI_ACR[AC97EN] bit)
After the SSI starts transmitting and receiving data after being configured in AC97 mode, the processor
needs to service the interrupts when they are raised (updates to command address/data or tag registers,
reading of received data, and writing more data for transmission). Further details regarding fixed and
variable mode implementation appear in the following sections.
While using AC97 in two-channel mode (TCH = 1), it is recommended that the received tag is not stored
in the Rx FIFO (TIF = 0). If you need to update the SSI_ATAG register and also issue a RD/WR command
(in a single frame), it is recommended that the SSI_ATAG register is updated prior to issuing a RD/WR
command.
25.4.1.5.1 AC97 Fixed Mode (SSI_ACR[FV]=0)
In fixed mode of operation, SSI transmits in accordance with the frame rate divider bits that decide the
number of frames for which the SSI should be idle, after operating for one frame. The following shows the
slot assignments in a valid transmit frame:
• Slot 0: The tag value (written by the user program)
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MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor