Freescale Semiconductor MCF52277 Reference Manual page 125

The RAMBAR contains several control fields. These fields are shown in
Rc[11:0]: 0x0C05 (RAMBAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
R
W
Reset U U U U U U U U U U U U U U U 0 0 0 0 0
Field
31–17 Base Address. Defines the 0-modulo-128K base address of the SRAM module. By programming this field,
BA the SRAM may be located on any 128-Kbyte boundary within the processor's 256-Mbyte address space.
For proper operation, the base address must be set to between 0x8000_0000 and 0x8FFE_0000.
16–12 Reserved, must be cleared.
11–10 Priority Bit. PRIU determines if the SRAM backdoor or CPU has priority in the upper 128K bank of memory.
PRIU PRIL determines if the SRAM backdoor or CPU has priority in the lower 128K bank of memory. If a bit is
PRIL set, the CPU has priority. If a bit is cleared, the SRAM backdoor has priority. Priority is determined according
to the following table:
Note: The recommended setting (maximum performance) for the priority bits is 00.
9 Backdoor Enable. Allows access by non-core bus masters via the SRAM backdoor on the crossbar switch
BDE 0 Non-core crossbar switch master access to memory is disabled.
1 Non-core crossbar switch master access to memory is enabled.
8 Write Protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access
WP from the core generates an access error exception to the ColdFire processor core.
0 Allows core read and write accesses to the SRAM module
1 Allows only core read accesses to the SRAM module
Note: This bit does not affect non-core write accesses.
7 Reserved, must be cleared.
6 Backdoor Write Protect. Allows only read accesses from the non-core bus masters. When this bit is set, any
BWP attempted write access from the non-core bus masters on the backdoor terminates the bus transfer with an
access error.
0 Allows read and write accesses to the SRAM module from non-core masters.
1 Allows only read accesses to the SRAM module from non-core masters.
Freescale Semiconductor
BA
Figure 6-1. SRAM Base Address Register (RAMBAR)
Table 6-2. RAMBAR Field Descriptions
PRIU,PRIL Upper Bank Priority
00
01
10
11
MCF52277 Reference Manual, Rev. 1
11 10
0 0 0 0 0
PRIU PRIL BDE WP
0 0
Description
Lower Bank Priority
SRAM Backdoor
SRAM Backdoor
CPU
CPU
Static RAM (SRAM)
Figure 6-1.
Access: User write-only
9 8 7 6 5 4
0
BWP C/I SC SD UC UD V
1 U 0 0 U U
SRAM Backdoor
CPU
SRAM Backdoor
CPU
Debug read/write
3 2 1 0
U U U 0
6-3