Freescale Semiconductor MCF52277 Reference Manual page 353

row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access,
followed by the read to the SDRAM.
The / and
PALL PRE ACTV
data movement.
To truncate a burst read when only a single read is needed, the memory controller issues the
burst-terminate command. With SDR memory, the data masks are negated throughout the entire read size.
With DDR memory, the data masks are asserted high throughout the entire read size; but DDR memory
ignores the data masks during reads.
19.5.1.3 Write Command (
When the memory controller receives a write request via the internal bus, it first checks the row and bank
of the new access. If the address falls within the active row of an active bank, it is a page hit, and the
is issued as soon as possible (pending any delays required by previous commands). If the address is within
the inactive bank, the memory controller issues an ACTV followed by the write command. If the address
is not within the active row of an active bank, the memory controller issues a PRE command to close the
active row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access,
followed by the
WRITE
The PALL/PRE and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going
data movement.
In SDR mode, the memory controller issues the burst terminate command to truncate burst write for a
single write. This is not the case for DDR system. With SDR and DDR memory, a read command can be
issued overlapping the masked beats at the end of a previous single write of the case CS; the read command
aborts the remaining (unnecessary) write beats.
19.5.1.4 Burst-Terminate Command (
SDRAMs are burst-only devices, but provide mechanisms to truncate a burst if all of the beats are not
needed. The burst-terminate command truncates read bursts (SDR and DDR) and write bursts (SDR). To
truncate a burst write for DDR, the read command can abort the remaining unnecessary write beats. This
method also works when in SDR mode. The most recently registered read or write command prior to the
burst terminate command is truncated. The active page remains open.
19.5.1.5 Precharge-All-Banks (
The precharge command puts SDRAM into an idle state. The SDRAM must be in this idle state before a
REF, , , or
LMR LEMR ACTV
The memory controller issues the precharge command only when necessary for one of these conditions:
• Access to a new row
• Refresh interval elapsed
• Software commanded precharge during device initialization
Freescale Semiconductor
commands (if necessary) can sometimes be issued in parallel with an on-going
)
WRITE
command to the SDRAM.
PALL
command to open a new row within a particular bank can be issued.
MCF52277 Reference Manual, Rev. 1
)
BST
) and Selected-Bank (
SDRAM Controller (SDRAMC)
) Commands
PRE
WRITE
19-23