Freescale Semiconductor MCF52277 Reference Manual page 577

If TXBIT0 is cleared and the word length is less than 16 bits, data occupies
the most significant portion of the lower 16 bits of the transmit register.
When SSI_TCR[SHFD] is cleared, data is shifted out of this register with the most significant bit (msb)
first. If this bit is set, the least significant bit (lsb) is shifted out first. The following figures show the
transmitter loading and shifting operation. They illustrate some possible values for WL, which can be
extended for the other values.
16 bits
20 bits
24 bits
SSI_TXD
Figure 25-5. Transmit Data Path (TXBIT0=0, TSHFD=0) (msb Alignment)
31
16 bits
20 bits
24 bits
31
TXSR
Figure 25-6. Transmit Data Path (TXBIT0=0, TSHFD=1) (msb Alignment)
Freescale Semiconductor
31
31
16 bits
12 bits
16 bits
MCF52277 Reference Manual, Rev. 1
NOTE
15 11
12 bits
12 bits
15 11 7
15 11 7
20 bits 24 bits 12 bits
Synchronous Serial Interface (SSI)
7 0
SSI_TX
0
TXSR
0
SSI_TX
0
SSI_TXD
25-9