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Debug Module
•
Results are returned in the two serial transfer cycles after the memory access completes. For any
command performing a byte-sized memory read operation, the upper 8 bits of the response data are
undefined and the referenced data is returned in the lower 8 bits. The next command's opcode is
sent to the debug module during the final transfer. If a bus error terminates a memory or register
access, error status (S = 1, DATA = 0x0001) returns instead of result data.
32.5.3.3
Command Set Descriptions
The following sections describe the commands summarized in
The BDM status bit (S) is 0 for normally completed commands. S is set for
illegal commands, not-ready responses, and transfers with bus-errors.
Section 32.5.2, "BDM Serial
format.
Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any
revision level perform a
32.5.3.3.1
Read A/D Register (
Read the selected address or data register and return the 32-bit result. A bus error response is returned if
the CPU core is not halted.
Command/Result Formats:
15
14
Command
Result
Command Sequence:
Operand Data:
Result Data:
32-26
Interface," describes the receive packet
and return an illegal command response.
NOP
/
RAREG
13
12
11
10
0x2
0x1
Figure 32-18.
RAREG
RAREG/RDREG
???
Figure 32-19.
RAREG
None
The contents of the selected register are returned as a longword value,
most-significant word first.
MCF52277 Reference Manual, Rev. 1
Table
NOTE
)
RDREG
9
8
7
6
0x8
D[31:16]
D[15:0]
/
Command Format
RDREG
XXX
NEXT CMD
MS RESULT
LS RESULT
XXX
NEXT CMD
BERR
'NOT READY'
/
Command Sequence
RDREG
32-20.
5
4
3
2
A/D
Register
Freescale Semiconductor
1
0
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