Freescale Semiconductor MCF52277 Reference Manual page 63

Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.
— One 16-bit mask register (MASK)
— One 32-bit Status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
The supervisor-programming model is intended to be used only by system control software to implement
restricted operating system functions, I/O control, and memory management. All accesses that affect the
control features of ColdFire processors are in the supervisor programming model, which consists of
registers available in user mode as well as the following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
• 32-bit access control registers (ACR0, ACR1)
• One 32-bit memory base address register (RAMBAR)
1
BDM
Load: 0x080 Data Register 0 (D0)
Store: 0x180
Load: 0x081 Data Register 1 (D1)
Store: 0x181
Load: 0x082–7 Data Register 2–7 (D2–D7)
Store: 0x182–7
Load: 0x088–8E Address Register 0–6 (A0–A6)
Store: 0x188–8E
Load: 0x08F Supervisor/User A7 Stack Pointer (A7)
Store: 0x18F
0x804 MAC Status Register (MACSR)
0x805 MAC Address Mask Register (MASK)
0x806, 0x809, MAC Accumulators 0–3 (ACC0–3)
0x80A, 0x80B
0x807 MAC Accumulator 0,1 Extension Bytes
(ACCext01)
0x808 MAC Accumulator 2,3 Extension Bytes
(ACCext23)
0x80E Condition Code Register (CCR)
Freescale Semiconductor
Table 3-1. ColdFire Core Programming Model
Register
Supervisor/User Access Registers
MCF52277 Reference Manual, Rev. 1
Width
Access Reset Value
(bits)
32 R/W 0xCF20_6089
32 R/W 0x1500_1090
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W 0x0000_0000
32 R/W 0xFFFF_FFFF
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
8 R/W Undefined
ColdFire Core
Written with
Section/Page
MOVEC
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