External Signal Description - Freescale Semiconductor MCF52277 Reference Manual

DMA Serial Peripheral Interface (DSPI)
29.1.4.4 Debug Mode
Debug mode is used for system development and debugging. If the device enters debug mode while the
DSPI_MCR[FRZ] bit is set, the DSPI halts operation on the next frame boundary. If the device enters
debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the
module-specific mode and configuration of the DSPI. See
29.2

External Signal Description

29.2.1 Signal Overview
Table 29-1 lists the DSPI signals.
Name
DSPI_PCS0/SS
DSPI_PCS[2,4]
DSPI_SIN
DSPI_SOUT
DSPI_SCK
29.2.2 Peripheral Chip Select/Slave Select (DSPI_PCS0/SS)
In master mode, the DSPI_PCS0 signal is a peripheral chip select output that selects the slave device to
which the current transmission is intended. In slave mode, the DSPI_SS signal is a slave select input signal
allowing an SPI master to select the DSPI as the target for transmission.
29.2.3 Peripheral Chip Selects 2,4 (DSPI_PCS[2,4])
The DSPI_PCS[2,4] signals are peripheral chip select output signals in master mode. In slave mode, these
signals are not used.
29.2.4 Serial Input (DSPI_SIN)
DSPI_SIN is a serial data input signal.
29.2.5 Serial Output (DSPI_SOUT)
DSPI_SOUT is a serial data output signal.
29-4
Table 29-1. DSPI Signal Properties
Master Mode
Peripheral chip select 0
Peripheral chip select 2,4
Serial data in
Serial data out
Serial clock
MCF52277 Reference Manual, Rev. 1
Figure 29-12 for a state diagram.
Function
I/O Slave Mode
Output Slave select
Output Unused
Input Serial data in
Output Serial data out
Output Serial clock
I/O
Input
—
Input
Output
Input
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