Introduction - Freescale Semiconductor MCF52277 Reference Manual

Chapter 30
UART Modules
30.1

Introduction

This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and
includes programming examples.
The designation n appears throughout this section to refer to registers or
signals associated with one of the three identical UART modules: UART0,
UART1, or UART2.
30.1.1 Overview
The internal bus clock can clock each of the three independent UARTs, eliminating the need for an external
UART clock. As Figure 30-1
• Serial communication channel
• Programmable clock generation
• Interrupt control logic and DMA request logic
• Internal channel control logic
Interrupt Request
(to Interrupt Controller)
Transmit DMA Request
Receive DMA Request
(To DMA Controller)
Freescale Semiconductor
NOTE
shows, each UART module interfaces directly to the CPU and consists of:
Internal Bus
UART Registers
Internal Channel
Control Logic
Interrupt Control
Logic
DMA Request
Logic
Figure 30-1. UART Block Diagram
MCF52277 Reference Manual, Rev. 1
UART
Serial
Communications
Channel
Programmable
Clock
Generation
UnCTS
UnRTS
UnRXD
UnTXD
Internal Bus Clock (f )
sys/2
or External Clock (DTnIN)
30-1