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28.4
Initialization/Application Information
The general-purpose timer modules typically, but not necessarily, follow this program order:
•
The DTMRn and DTXMRn registers are configured for the desired function and behavior.
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTnIN
— Configure DTnOUT output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
•
The DTMRn[CLK] register is configured to select the clock source to be routed to the prescaler.
— Internal bus clock (can be divided by 1 or 16)
— DTnIN, the maximum value of DTnIN is 1/5 of the internal bus clock, as described in the
device's electrical characteristics
DTnIN may not be configured as a clock source when the timer capture
mode is selected or indeterminate operation results.
•
The 8-bit DTMRn[PS] prescaler value is set.
•
Using DTMRn[RST], counter is cleared and started.
•
Timer events are managed with an interrupt service routine, a DMA request, or by a software
polling mechanism.
28.4.1
Code Example
The following code provides an example of how to initialize and use DMA Timer0 for counting time-out
periods.
DTMR0 EQU 0xFC07_0000 ;Timer0 mode register
DTMR1 EQU 0xFC07_4000 ;Timer1 mode register
DTRR0 EQU 0xFC07_0004 ;Timer0 reference register
DTRR1 EQU 0xFC07_4004 ;Timer1 reference register
DTCR0 EQU 0xFC07_0008 ;Timer0 capture register
DTCR1 EQU 0xFC07_4008 ;Timer1 capture register
DTCN0 EQU 0xFC07_000C ;Timer0 counter register
DTCN1 EQU 0xFC07_400C ;Timer1 counter register
DTER0 EQU 0xFC07_0003 ;Timer0 event register
DTER1 EQU 0xFC07_4003 ;Timer1 event register
* TMR0 is defined as: *
*[PS] = 0xFF,
divide clock by 256
*[CE] = 00
disable capture event output
*[OM] = 0
output=active-low pulse
*[ORRI] = 0,
disable ref. match output
*[FRR] = 1,
restart mode enabled
*[CLK] = 10,
internal bus clock/16
*[RST] = 0,
timer0 disabled
move.w #0xFF0C,D0
move.w D0,TMR0
Freescale Semiconductor
NOTE
MCF52277 Reference Manual, Rev. 1
DMA Timers (DTIM0–DTIM3)
28-9
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