Freescale Semiconductor MCF52277 Reference Manual page 756

Debug Module
contents of the breakpoint registers are compared with the processor's program counter register when TDR
is configured appropriately.
The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the
Set Descriptions".
DRc[4:0]: 0x08 (PBR0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Field
31–0 PC Breakpoint Address. The address to be compared with the PC as a breakpoint trigger.
Address Note: PBR0[0] should always be loaded with a 0.
DRc[4:0]: 0x18 (PBR1)
0x1A (PBR2)
0x1B (PBR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 0
Field
31–1 PC Breakpoint Address. The 31-bit address to be compared with the PC as a breakpoint trigger.
Address
0 Valid Bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
V 0 PBR is disabled.
1 PBR is enabled.
Figure 32-9 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and
via the BDM port using the
32-16
command using values shown in
WDMREG
Figure 32-7. PC Breakpoint Register (PBR0)
Table 32-10. PBR0 Field Descriptions
Figure 32-8. PC Breakpoint Register n (PBRn)
Table 32-11. PBRn Field Descriptions
command. PBMR only masks PBR0.
WDMREG
MCF52277 Reference Manual, Rev. 1
Address
Description
Address
Description
Section 32.5.3.3, "Command
Access: Supervisor write-only
BDM write-only
8 7 6 5 4 3 2 1
Access: Supervisor write-only
BDM write-only
8 7 6 5 4 3 2 1
Freescale Semiconductor
0
0
V