Freescale Semiconductor MCF52277 Reference Manual page 710

UART Modules
UnTXD
Transmitter
Enabled
USRn[TXRDY]
internal
module
select
3
UnCTS
4
UnRTS
1
Cn = transmit characters
2
W = write
3
UMR2n[TXCTS] = 1
4
UMR2n[TXRTS] = 1
30.4.2.2 Receiver
The receiver is enabled through its UCRn, as described in
(UCRn)."
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on UnRXD, the state of
UnRXD is sampled eight times on the edge of the bit time clock starting one-half clock after the transition
(asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If
UnRXD is sampled high, start bit is invalid and the search for the valid start bit begins again.
If UnRXD remains low, a valid start bit is assumed. The receiver continues sampling the input at one-bit
time intervals at the theoretical center of the bit until the proper number of data bits and parity, if any, is
assembled and one stop bit is detected. Data on the UnRXD input is sampled on the rising edge of the
programmed clock source. The lsb is received first. The data then transfers to a receiver holding register
and USRn[RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the
receiver holding register are cleared.
After the stop bit is detected, receiver immediately looks for the next start bit. However, if a non-zero
character is received without a stop bit (framing error) and UnRXD remains low for one-half of the bit
period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error,
30-20
C1 in transmission
1
C1
2
W W
1
C1 C2
Manually asserted
by - command
BIT SET
Figure 30-19. Transmitter Timing Diagram
MCF52277 Reference Manual, Rev. 1
C2 C3 Break
W W W
C3 Start C4 Stop
break
Section 30.3.5, "UART Command Registers
C4
W W
C5
break not
transmitted
Manually
asserted
Freescale Semiconductor
C6
W
C6