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Crossbar Switch (XBS)
The modules are assigned to the numbered ports on the crossbar switch in the below table.
Crossbar Port
Master 0 (M0)
Master 1 (M1)
Master 4 (M4)
Master 6 (M6)
Master 7 (M7)
Crossbar Port
Slave 1 (S1)
Slave 4 (S4)
Slave 7 (S7)
1
Unused address spaces are reserved.
2
See the various peripheral chapters for their memory maps. Any unused space by these
peripherals within this memory range is reserved and must not be accessed.
This memory map provides two disjoint regions mapped to the FlexBus
controller to support glueless connections to external memories (e.g., flash
and SRAM) as well as a second space with one (or more) unique
chip-selects that can be used for non-cacheable, non-memory devices
(addresses 0xC000_0000–0xDFFF_FFFF). Additionally, this mapping is
selected because it easily maps into the ColdFire access control registers,
which provide a coarse association between memory addresses and their
attributes (e.g., cacheable, non-cacheable). For this device, one possible
configuration defines the default memory attribute as non-cacheable, and
one ACR then identifies cacheable addresses, e.g., ADDR[31] equals 0
identifies the cacheable space.
13.2
Features
The crossbar switch includes these distinctive features:
•
Symmetric crossbar bus switch implementation
— Allows concurrent accesses from different masters to different slaves
— Slave arbitration attributes configured on a slave by slave basis
•
32 bits wide and supports byte, word (2 byte), longword (4 byte), and 16 byte burst transfers
13-2
Table 13-1. Crossbar Switch Master/Slave Assignments
Master Modules
Slave Modules
Module
Flexbus
SDRAM Controller
Internal SRAM Backdoor
Other on-chip slave peripherals 0xF000_0000–0xFFFF_FFFF
MCF52277 Reference Manual, Rev. 1
Module
ColdFire Core
eDMA Controller
LCD Controller
USB On-the-Go
Serial Boot
Address Range
0x0000_0000–0x3FFF_FFFF &
0xC000_0000–0xDFFF_FFFF
0x4000_0000–0x7FFF_FFFF
0x8000_0000–0x8FFF_FFFF
NOTE
1
2
Freescale Semiconductor
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