Freescale Semiconductor MCF52277 Reference Manual page 323

transfer start (FB_TS) is asserted.
two clocks of address setup.
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-20. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)
FB_D[31:X]
FB_CSn, FB_BE/BWEn
Figure 18-21. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
Freescale Semiconductor
Figure 18-20
S0 AS
ADDR[31:X]
S0
FB_CLK
FB_A[23:0]
ADDR[31:X]
FB_R/W
FB_TS
FB_OE
FB_TA
MCF52277 Reference Manual, Rev. 1
and Figure 18-21 show read- and write-bus cycles with
S1 S2
ADDR[23:0]
DATA
AS S1 S2
ADDR[23:0]
DATA
S3 S0
S3 S0
FlexBus
18-21