Freescale Semiconductor MCF52277 Reference Manual page 763

Command Mnemonic
Read A/D /
RAREG
register
RDREG
Write A/D /
WAREG
register
WDREG
Read
READ
memory
location
Write
WRITE
memory
location
Dump
DUMP
memory
block
Fill memory
FILL
block
Resume
GO
execution
No operation
NOP
Output the _
SYNC PC
current PC
Read control
RCREG
register
Write control
WCREG
register
Read debug
RDMREG
module
register
Write debug
WDMREG
module
register
1
General command effect and/or requirements on CPU operation:
- Halted: The CPU must be halted to perform this command.
- Steal: Command generates bus cycles that can be interleaved with bus accesses.
- Parallel: Command is executed in parallel with CPU activity.
2
0x4 is a three-bit field.
Freescale reserves unassigned command opcodes. All unused command formats within any revision level
perform a and return the illegal command response.
NOP
Freescale Semiconductor
Table 32-20. BDM Command Summary
Description
Read the selected address or data register and
return the results through the serial interface.
Write the data operand to the specified address or
data register.
Read the data at the memory location specified by
the longword address.
Write the operand data to the memory location
specified by the longword address.
Used with to dump large blocks of memory. An
READ
initial executes to set up the starting address
READ
of the block and to retrieve the first result. A
command retrieves subsequent operands.
Used with to fill large blocks of memory. An
WRITE
initial executes to set up the starting address
WRITE
of the block and to supply the first operand. A
command writes subsequent operands.
The pipeline is flushed and refilled before resuming
instruction execution at the current PC.
Perform no operation; may be used as a null
command.
Capture the current PC and display it on the
PST/DDATA outputs.
Read the system control register.
Write the operand data to the system control
register.
Read the debug module register.
Write the operand data to the debug module
register.
MCF52277 Reference Manual, Rev. 1
CPU
Section/Page
1
State
Halted 32.5.3.3.1/32-26
Halted 32.5.3.3.2/32-27
Steal 32.5.3.3.3/32-27
Steal 32.5.3.3.4/32-29
Steal 32.5.3.3.5/32-30
DUMP
Steal 32.5.3.3.6/32-32
FILL
Halted 32.5.3.3.7/32-33
Parallel 32.5.3.3.8/32-34
Parallel 32.5.3.3.9/32-34
Halted 32.5.3.3.10/32-35
Halted 32.5.3.3.13/32-37
Parallel 32.5.3.3.14/32-38
Parallel 32.5.3.3.15/32-39
Debug Module
Command
(Hex)
0x218 {A/D,
Reg[2:0]}
0x208 {A/D,
Reg[2:0]}
0x1900—byte
0x1940—word
0x1980—lword
0x1800—byte
0x1840—word
0x1880—lword
0x1D00—byte
0x1D40—word
0x1D80—lword
0x1C00—byte
0x1C40—word
0x1C80—lword
0x0C00
0x0000
0x0001
0x2980
0x2880
2
0x2D {0x4
DRc[4:0]}
2
0x2C {0x4
DRc[4:0]}
32-23