Memory Map/Register Definition - Freescale Semiconductor MCF52277 Reference Manual

SDRAM Controller (SDRAMC)
19.4

Memory Map/Register Definition

The SDRAM controller and its associated logic contain two sets of programming registers:
• SDRAM controller's control and configuration registers
• Chip-select configuration control registers
The slew rate for the SDRAM pins is controlled by a register in the pin
multiplexing and control module. See
Select Control Register (MSCR_SDRAM),"
Table 19-6 shows the SDRAM controller control and configuration registers. Unspecified memory spaces
are reserved for future use. Access to reserved space is prohibited. It is recommended to write 0 to reserved
space. Reads from a write-only bit return 0.
Address
0xFC0B_8000 SDRAM Mode/Extended Mode Register (SDMR)
0xFC0B_8004 SDRAM Control Register (SDCR)
0xFC0B_8008 SDRAM Configuration Register 1 (SDCFG1)
0xFC0B_800C SDRAM Configuration Register 2 (SDCFG2)
0xFC0B_8110 SDRAM Chip Select 0 Configuration (SDCS0)
0xFC0B_8114 SDRAM Chip Select 1 Configuration (SDCS1)
19.4.1 SDRAM Mode/Extended Mode Register (SDMR)
The SDMR (Figure 19-5) writes to the mode and extended mode registers physically residing within the
SDRAM chips. These registers must be programmed during SDRAM initialization. See
"Initialization/Application
Address: 0xFC0B_8000 (SDMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
R
BK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19-14
Table 19-6. SDRAMC Memory Map
Register
Information" for more information on the initialization sequence.
AD
Figure 19-5. SDRAM-Mode/Extended-Mode Register (SDMR)
MCF52277 Reference Manual, Rev. 1
NOTE
Section 14.3.7, "SDRAM Mode
for more details.
Width
(bits)
32
32
32
32
32
32
Access: SDCR[MODE_EN] = 0 User read-only
SDCR[MODE_EN] = 1 User read/write
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CMD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access Reset Value Section/Page
R/W 0x0000_0000 19.4.1/19-14
R/W 0x0000_0000 19.4.2/19-15
R/W 0x0000_0000 19.4.3/19-17
R/W 0x0000_0000 19.4.4/19-19
R/W 0x0000_0000 19.4.5/19-20
R/W 0x0000_0000 19.4.5/19-20
Section 19.6,
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