External Signal Description - Freescale Semiconductor MCF52277 Reference Manual

• Shuts down the system clocks
The bus interface unit continues to operate, enabling the CPU to access memory-mapped registers, except
the free-running timer, the error counter register, and the message buffers, which cannot be accessed when
the module is disabled. Exiting from this mode is done by negating the MDIS bit, which resumes the clocks
and negate the LPMACK bit.
23.1.3.4 Loop-back Mode
The module enters this mode when the LPB bit in the control register is set. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN
output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting and
treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception
of its own message. Transmit and receive interrupts are generated.
23.1.3.5 Listen-only Mode
In listen-only mode, transmission is disabled, all error counters are frozen and the module operates in a
CAN error passive mode. Only messages acknowledged by another CAN station are received. If FlexCAN
detects a message that has not been acknowledged, it flags a BIT0 error (without changing the REC), as if
it was trying to acknowledge the message. Because the module does not influence the CAN bus in this
mode, the device is capable of functioning like a monitor or for automatic bit-rate detection.
23.2

External Signal Description

Each FlexCAN module has two I/O signals connected to the external MPU pins: CANTX and CANRX.
CANTX transmits serial data to the CAN bus transceiver, while CANRX receives serial data from the
CAN bus transceiver.
23.3 Memory Map/Register Definition
The FlexCAN module address space is split into 128 bytes starting at the base address, 256 bytes starting
at the base address + 0x80, and 256 bytes starting at the base address + 0x880. Out of the lower 128 bytes,
only part is occupied by various registers. The second block of 256 bytes are fully used for the message
buffer structures, as described in
by the individual masking registers.
Address
FlexCAN
0xFC02_0000 FlexCAN Module Configuration
Register (CANMCR)
Freescale Semiconductor
Section 23.3.9, "Message Buffer Structure."
Table 23-1. FlexCAN Memory Map
Width
Register
(bits)
Supervisor-only Access Registers
32
MCF52277 Reference Manual, Rev. 1
Affected Affected
by Hard by Soft Access
Reset Reset
Y Y R/W
FlexCAN
The upper 256 bytes is used
Reset Value Section/Page
0xD890_000F 23.3.1/23-6
23-5