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Table 32-17. Address, Access Size, and Operand Data Location
32.5
Background Debug Mode (BDM)
The ColdFire family implements a low-level system debugger in the microprocessor in a dedicated
hardware module. Communication with the development system is managed through a dedicated,
high-speed serial command interface. Although some BDM operations, such as CPU register accesses,
require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the
processor is running.
BDM is useful because:
•
In-circuit emulation is not needed, so physical and electrical characteristics of the system are not
affected.
•
BDM is always available for debugging the system and provides a communication link for
upgrading firmware in existing systems.
•
Provides high-speed cache downloading (500 Kbytes/sec), especially useful for flash
programming
•
Provides absolute control of the processor, and thus the system. This feature allows quick hardware
debugging with the same tool set used for firmware development.
32.5.1
CPU Halt
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation
requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of
priority:
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint trigger can generate a pending halt condition similar to the assertion of
BKPT. This type of halt is always first marked as pending in the pocessor, which samples for
pending halt and interrupt conditions once per instruction. When a pending condition is asserted,
the processor halts execution at the next sample point. See
Freescale Semiconductor
Address[1:0]
Access Size
00
Byte
01
Byte
10
Byte
11
Byte
0x
Word
1x
Word
xx
Longword
MCF52277 Reference Manual, Rev. 1
Operand Location
D[31:24]
D[23:16]
D[15:8]
D[7:0]
D[31:16]
D[15:0]
D[31:0]
Section 32.6.1, "Theory of
Debug Module
Operation".
32-19
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