Freescale Semiconductor MCF52277 Reference Manual page 392

Universal Serial Bus Interface – On-The-Go Module
Field
6 Force Port Resume. This bit is not-EHCI compatible.
FPR 0 No resume (K-state) detected/driven on port.
1 Resume detected/driven on port.
Host mode:
Software sets this bit to drive resume signaling. The controller sets this bit if a J-to-K transition is detected while
the port is in suspend state (PE = SUSP = 1), which in turn sets the USBSTS[PCI] bit. This bit automatically
clears after the resume sequence is complete. This behavior is different from EHCI where the host controller
driver is required to clear this bit after the resume duration is timed in the driver.
When the controller owns the port, the resume sequence follows the defined sequence documented in the USB
Specification Revision 2.0. The resume signaling (full-speed K) is driven on the port as long as this bit remains
set. This bit remains set until the port switches to the high-speed idle. Clearing this bit has no affect because the
port controller times the resume operation to clear the bit the port control state switches to HS or FS idle.
This field is cleared if the PP bit is cleared in host mode.
Device mode:
After the device is in suspend state for 5 ms or more, software must set this bit to drive resume signaling before
clearing. The device controller sets this bit if a J-to-K transition is detected while port is in suspend state, which
in turn sets the USBSTS[PCI] bit. The bit is cleared when the device returns to normal operation.
5 Over-current change. Indicates a change to the OCA bit. Software clears this bit by writing a 1. For host mode, the
OCC user can provide over-current detection to the USBn_PWRFAULT signal for this condition. For device-only
implementations, this bit must always be cleared.
0 No over-current.
1 Over-current detect.
4 Over-current active. This bit automatically transitions from 1 to 0 when the over-current condition is removed. For
OCA host/OTG implementations, the user can provide over-current detection to the USBn_PWRFAULT signal for this
condition. For device-only implementations, this bit must always be cleared.
0 Port not in over-current condition.
1 Port currently in over-current condition.
3 Port enable/disable change. For the root hub, this bit gets set only when a port is disabled due to disconnect on the
PEC port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification).
Software clears this by writing a 1 to it.
In device mode, the device port is always enabled. (This bit is zero).
0 No change.
1 Port disabled.
This field is cleared if the PP bit is cleared.
2 Port enabled/disabled.
PE Host mode:
Ports can only be enabled by the controller as a part of the reset and enable sequence. Software cannot enable
a port by setting this bit. A fault condition (disconnect event or other fault condition) or host software can disable
ports. The bit status does not change until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host and bus events.
When the port is disabled, downstream propagation of data is blocked except for reset. This field is cleared if the
PP bit is cleared in host mode.
Device mode:
The device port is always enabled. (This bit is set).
20-34
Table 20-32. PORTSC1 Field Descriptions (continued)
MCF52277 Reference Manual, Rev. 1
Description
Freescale Semiconductor