Rx Fifo Buffering Mechanism - Freescale Semiconductor MCF52277 Reference Manual

The TX FIFO counter field (TXCTR) in the DSPI status register (DSPI_SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data
transfers into the shift register from the TX FIFO. For more information on DSPI_SR, refer to
Section 29.3.4, "DSPI Status Register (DSPI_SR)."
The DSPI_SR[TXNXTPTR] field indicates which TX FIFO entry is transmitted during the next transfer.
The TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For
example, TXNXTPTR equal to two means DSPI_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field increments every time SPI data transfers from TX FIFO to shift register.
29.4.2.4.1 Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPI_PUSHR register. When the TX FIFO is not full, the TX FIFO fill flag, DSPI_SR[TFFF], is set. The
TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates that a write to
DSPI_PUSHR is complete. Host software writing a 1 to the DSPI_SR[TFFF] bit can also clear the TFFF
bit. The TFFF can generate a DMA request or an interrupt request. See
Fill Interrupt or DMA Request (TFFF),"
The DSPI ignores attempts to push data to a full TX FIFO; in other words, the state of the TX FIFO is
unchanged and no error condition is indicated.
29.4.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
decrements by one. At the end of a transfer, the DSPI_SR[TCF] bit is set to indicate completion of a
transfer. The TX FIFO is flushed by writing a 1 to the DSPI_MCR[CLR_TXF] bit.
If an external SPI bus master initiates a transfer with a DSPI slave while the slave's DSPI TX FIFO is
empty, the slave's transmit FIFO underflow flag, DSPI_SR[TFUF], is set. See
FIFO Underflow Interrupt Request
29.4.2.5

RX FIFO Buffering Mechanism

The RX FIFO functions as a buffer for data received on the DSPI_SIN pin. The RX FIFO holds 16
received SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the
received data in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the
RX FIFO by reading the DSPI_POPR register. RX FIFO entries can only be removed from the RX FIFO
by reading the DSPI_POPR or by flushing the RX FIFO. For more information on the DSPI_POPR, refer
to Section 29.3.7, "DSPI POP RX FIFO Register (DSPI_POPR)."
The RX FIFO counter field, DSPI_SR[RXCTR], indicates the number of valid entries in the RX FIFO.
The RXCTR is updated every time the DSPI _POPR is read or SPI data is copied from the shift register to
the RX FIFO.
The DSPI_SR[POPNXTPTR] field points to the RX FIFO entry returned when the DSPI_POPR is read.
The POPNXTPTR contains the positive, 32-bit word offset from DSPI_RXFR0. For example,
Freescale Semiconductor
for details.
(TFUF),"for details.
MCF52277 Reference Manual, Rev. 1
DMA Serial Peripheral Interface (DSPI)
Section 29.4.6.2, "Transmit FIFO
Section 29.4.6.4, "Transmit
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