Freescale Semiconductor MCF52277 Reference Manual page 337

Table 19-3. SDRAM Address Multiplexing in 32-bit Bus Mode (continued)
Device Configuration
8M x 32 bit
16M x 16 bit
256 Mbits
32M x 8 bit
64M x 4 bit
16M x 32 bit
512 Mbits 32 M x 16 bit
64M x 8 bit
32M x 32 bit
1 Gbits
64M x 16 bit
2 Gbits 64M x 32 bit
1
All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.
2
All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an
extra bit CA10 to control the precharge option.
Freescale Semiconductor
Row bit x SDCR
Col bit x [ADDR_
Banks MUX] 27
12 x 9 x 4 00 —
13 x 8 x 4 01 —
12 x 10 x 4 00 —
13 x 9 x 4 01 —
14 x 8 x 4 10 —
12 x 11 x 4 00 —
13 x 10 x 4 01 —
14 x 9 x 4 10 —
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
12 x 10 x 4 00 —
13 x 9 x 4 01 —
14 x 8 x 4 10 —
12 x 11 x 4 00 —
13 x 10 x 4 01 —
14 x 9 x 4 10 —
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
12 x 11 x 4 00 —
13 x 10 x 4 01 —
14 x 9 x 4 10 —
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
MCF52277 Reference Manual, Rev. 1
Internal Address
26 25 24
— — CA8
— — RA12
— CA9 CA8
— CA8 RA12
— RA13 RA12
CA11 CA9 CA8 RA11-0 BA1-0
CA9 CA8 RA12
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
— CA9 CA8
— CA8 RA12
— RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12 RA11-0 BA1-0
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
RA11-0 BA1-0
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12 RA11-0 BA1-0
CA8 RA13 RA12
SDRAM Controller (SDRAMC)
23–12 11–10 9–2
CA7-0
CA7-0
CA7-0
CA7-0
19-7