Freescale Semiconductor MCF52277 Reference Manual page 206

Crossbar Switch (XBS)
XBS_CRSn[RO] bit is set, the XBS_PRSn register can only be read; attempts to write to it have no effect
on XBS_PRSn and result in a bus-error response to the master initiating the write.
Additionally, no two available master ports may be programmed with the same priority level, including
reserved masters. Attempts to program two or more masters with the same priority level result in a
bus-error response (see
is not updated.
Address: 0xFC00_4100 (XBS_PRS1)
0xFC00_4400 (XBS_PRS4)
0xFC00_4700 (XBS_PRS7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0
M7
W
Reset 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Field
31 Reserved, must be cleared.
30–28 Master 7 (Serial Boot) priority. This field sets the arbitration priority for this port on the associated slave port.
M7 000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
011 This master has level 4 priority when accessing the slave port.
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 priority when accessing the slave port.
111 This master has level 8 (lowest) priority when accessing the slave port.
27 Reserved, must be cleared.
26–24 Master 6 (USB OTG) priority. See M7 description.
M6
23–19 Reserved, must be cleared.
18–16 Master 4 (LCD Controller) priority. See M7 description.
M4
15–7 Reserved, must be cleared.
6–4 Master 1 (eDMA) priority. See M7 description.
M1
3 Reserved, must be cleared.
2–0 Master 0 (ColdFire core) priority. See M7 description.
M0
13-4
Section 12.2.5, "SCM Interrupt Status Register
0 0 0 0 0 0
M6
Figure 13-2. XBS Priority Registers Slave n (XBS_PRSn)
Table 13-3. XBS_PRSn Field Descriptions
MCF52277 Reference Manual, Rev. 1
(SCMISR)") and the XBS_PRSn
0 0 0 0 0 0 0 0 0
M4
Description
Access: Supervisor read/write
8 7 6 5 4 3 2 1
0
M1 M0
Freescale Semiconductor
0