Freescale Semiconductor MCF52277 Reference Manual page 414

Universal Serial Bus Interface – On-The-Go Module
DCD software must maintain a state variable to differentiate between the defaultFS/HS state and the
address/configured states. Change of state from default to the address and configured states is part of the
enumeration process described in the device framework section of the USB 2.0 specification.
As a result of entering the address state, the DCD must program the device address register
(DEVICEADDR).
Entry into the configured state indicates that all endpoints to be used in the operation of the device have
been properly initialized by programming the EPCRn registers and initializing the associated queue heads.
20.5.3.2.1 Bus Reset
The host uses a bus reset to initialize downstream devices. When a bus reset is detected, USB OTG
controller renegotiates its attachment speed, resets the device address to 0, and notifies the DCD by
interrupt (assuming the USB reset interrupt enable is set). After a reset is received, all endpoints (except
endpoint 0) are disabled and the device controller cancels any primed transactions. The concept of priming
is clarified below, but when a reset is received, the DCD must perform:
1. Clear all setup token semaphores by reading the EPSETUPSR register and writing the same value
back to the EPSETUPSR register.
2. Clear all the endpoint complete status bits by reading the EPCOMPLETE register and writing the
same value back to the EPCOMPLETE register.
3. Cancel all primed status by waiting until all bits in the EPPRIME are 0 and then writing
0xFFFF_FFFF to EPFLUSH.
4. Read the reset bit in the PORTSCn register and make sure it remains active. A USB reset occurs
for a minimum of 3 ms and the DCD must reach this point in the reset clean-up before end of the
reset occurs, otherwise a hardware reset of the device controller is recommended (rare).
a) Setting USBCMD[RST] bit can perform a hardware reset.
A hardware reset causes the device to detach from the bus by clearing the
USBCMD[RS] bit. Therefore, the DCD must completely re-initialize the
USB OTG after a hardware reset.
5. Free all allocated dTDs because the device controller no longer executes them. If this is the first
time the DCD processes a USB reset event, it is likely w3a4no dTDs have been allocated.
6. At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a port change detect is indicated.
20-56
Table 20-49. Device Controller State Information Bits
Bit
DC Suspend (SLI)
USB Reset Received (URI)
Port Change Detect (PCI)
High-Speed Port (PSPD)
MCF52277 Reference Manual, Rev. 1
Register
USBSTS
USBSTS
USBSTS
PORTSCn
NOTE
Freescale Semiconductor