Freescale Semiconductor MCF52277 Reference Manual page 152

Power Management
interrupt can bring the device out of low-power mode. This system setup must meet the conditions
specified in Section 8.3.3, "Low-Power Modes,"
low-power mode.
8.3.4.7 Crossbar Switch
The crossbar switch is enabled during any low-power mode.
8.3.4.8 GPIO Ports
The GPIO ports are unaffected by entry into a low-power mode. These pins may impact low-power current
draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is
exited by a reset, the state of the I/O pins reverts to their default direction settings.
8.3.4.9 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input sources
and generating the interrupt to the processor is combinational to allow the ability to wake up the core
during low-power stop mode when all system clocks stop.
An interrupt request causes the processor to exit a low-power mode only if that interrupt's priority level is
at or above the level programmed in the interrupt priority mask field of the CPU's status register (SR) and
above the level programmed in the WCR[PRILVL]. The interrupt must also be enabled in the interrupt
controller's interrupt mask register as well as at the module from which the interrupt request would
originate.
8.3.4.10 Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to generate
interrupts (an edge transition or low level on an external pin) to exit the low-power modes.
In stop mode, no system clock is available to perform the edge detect function. Therefore, only the level
detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an
interrupt (if enabled) to exit stop mode.
8.3.4.11 eDMA Controller
In wait and doze modes, the eDMA controller can bring the device out of a low-power mode by generating
an interrupt upon completion of a transfer or upon an error condition. The completion of transfer interrupt
generates when DMA interrupts are enabled by the setting of a EDMA_INTR[INTn], and an interrupt is
generated when TCDn[DONE] is set. The interrupt upon error condition is generated when
EDMA_EEIR[EEIn] is set, and an interrupt generates when any of the EDMA_ESR bits become set.
The eDMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.
8-12
for the core watchdog interrupt to bring the part out of
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor