Freescale Semiconductor MCF52277 Reference Manual page 574

Synchronous Serial Interface (SSI)
Figure 25-2 shows the main SSI configurations. These ports support all transmit and receive functions with
continuous or gated clock as shown. Gated clock implementations do not require the use of the frame sync
port (SSI_FS).
SSI_TXD
SSI_RXD
SSI_BCLK
SSI_FS
SSI_MCLK
SSI_TXD
SSI_RXD
SSI_BCLK
SSI_FS
SSI_TXD
SSI_RXD
SSI_BCLK
SSI_TXD
SSI_RXD
SSI_BCLK
Figure 25-2. Synchronous SSI Configurations—Continuous and Gated Clock
Figure 25-3 shows an example of the port signals for an 8-bit data transfer. Continuous and gated clock
signals are shown, as well as the bit-length frame sync signal and the word-length frame sync signal. The
shift direction can be defined as msb first or lsb first, and there are other options on the clock and frame
sync.
Continuous
SSI_BCLK
SSI_FS
Early
SSI_FS
Gated
SSI_BCLK
SSI_TXD
SSI_RXD
Bit Length Frame Sync
Word Length Frame Sync
25-6
SSI Internal Continuous Clock
(RXDIR=0, TXDIR=1, TFDIR=1, SYN=1, MCE=1)
SSI I2S Master Mode
(I2S_Mode=01, MCE)
SSI External Continuous Clock
(RXDIR=0, TXDIR=0, TFDIR=0, SYN=1)
SSI I2S Slave Mode
(I2S_Mode=10)
SSI Internal Gated Clock
(RXDIR=1, TXDIR=1, SYN=1)
SSI External Gated Clock
(RXDIR=1, TXDIR=0, SYN=1)
2
7 6 5 4 3
8-bit Data
7 6 5 4 3 2
Figure 25-3. Serial Clock and Frame Sync Timing
MCF52277 Reference Manual, Rev. 1
1 0
1 0
7 6
7 6
Freescale Semiconductor