Interrupts - Freescale Semiconductor MCF52277 Reference Manual

For any configuration change/initialization, the FlexCAN must be in freeze mode (see
"Freeze Mode"). The following is a generic initialization sequence applicable to the FlexCAN module:
1. Initialize the CANMCR register
a) Enable individual filtering per MB and reception queue features by setting the BCC bit
2. Initialize all operation modes in the CANCTRL register.
a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW.
b) Select the S-clock rate by programming the PRESDIV field.
c) Select the internal arbitration mode via the LBUF bit.
3. Initialize message buffers.
a) The control/status word of all message buffers must be written as an active or inactive message
buffer.
b) All other entries in each message buffer should be initialized as required.
4. Initialize the RX individual mask registers for acceptance mask as needed.
5. Initialize FlexCAN interrupt handler.
a) Initialize the interrupt controller registers for any needed interrupts. See
Controller Modules,"
b) Set the required mask bits in the IMASK register (for all message buffer interrupts) and the
CANCTRL (for bus off and error interrupts).
6. Clear the CANMCR[HALT] bit. At this point, the FlexCAN attempts to synchronize with the CAN
bus.
23.4.1

Interrupts

There are 19 interrupt sources for the FlexCAN module. An interrupt for each of the 16 MBs. Plus, a
combined interrupt for all 16 MBs is generated by logically OR'ing all the interrupt sources from the MBs.
In this case, the CPU must read the IFLAG register to determine which MB caused the interrupt. The other
two interrupt sources (bus off and error) act in the same manner, and are located in the ERRSTAT register.
The bus off and error interrupt mask bits are located in the CANCTRL register.
Freescale Semiconductor
for more information.
MCF52277 Reference Manual, Rev. 1
FlexCAN
Section 23.1.3.2,
Chapter 15, "Interrupt
23-31