Freescale Semiconductor MCF52277 Reference Manual page 564

Pulse-Width Modulation (PWM) Module
DSync Revision
Version Date
— 30 Jun 2004 E Southers
— 14 Jul 2004 E Southers
— 20 Sept 2004 E Southers
— 22 Oct 2004 E Southers
— 17 Nov 2004 E Southers
— 12 May 2005 E Southers
— 16 Aug 2005 E Southers
— 15 Nov 2005 E Southers
— 26 Jan 2006 E Southers
—
— 7 Jul 2006 E Southers
— 25 Aug 2006
24-22
Table 24-17. Revision History (continued)
Description of Changes
Author
• Deleted duplicate
(EDS) • Corrected Section 24.1.1,
all six PWM channels" to "if all four PWM
channels"
• Added clarification to
"PWM Clock Select Register
(PWMCLK)"
• Corrected register name in equation in
Section 24.2.10, "PWM Channel Period
Registers (PWMPERn)"
• Added absolute value symbol around
duty cycle equation in
"PWM Channel Duty Registers
(PWMDTYn)".
• Renamed Section 24.3.1.1, "Prescaled
Clock (A or B)"
"Scaled Clock (SA or SB)"
• Fixed cross references in
Section 24.3.2.4, "PWM Timer
Counters"
• Added headings for left & center-aligned
output sections
• Fixed addresses for PWM Duty
(EDS) Registers in Figure 24-12
(EDS)
• Converted to SRS3.2 template
(EDS) • Added PWM=4 & PWM=6 condition tags
• Converted to pwm_8b8c block
(EDS) • Removed Tosca condition tag
• Completed PWM=odd conditional text
(EDS) for DF/ST.
• Corrected other conditional text
mistakes.
• Added width column to memory map
(EDS) table
(EDS)
• Corrected register addresses for DF/ST.
(EDS) Add a 0x20 offset to all.
(EDS)
M. • Added Kirin2e conditional tag and
Tsurikov assigned it to entries tagged for Kirin.
(MST)
MCF52277 Reference Manual, Rev. 1
Internal
Table 1-1
"Overview": "if
Section 24.2.3,
Section 24.2.11,
and Section 24.3.1.2,
Tosca Rev. 1
DF/ST Rev. 0
Kirin2e Rev. 2
Minime/DF/ST Rev. 1
Description of Changes
External
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Freescale Semiconductor