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Chip Configuration Module (CCM)
Pin(s) Affected
(none)
(none)
PLL's PCR[PFDR]
1
32-bit port size is not available when DRAMSEL = 0.
9.4.2
Boot Configuration
The FB_CS0 chip select pin selects an external boot device during reset configuration if:
•
It is not in serial boot mode
•
It is in serial boot mode and the boot code is not in SPI memory
•
You choose not to program FB_CS0 to be a GPIO after serial boot is complete
The valid (V) bit in the CSMR0 register is ignored and FB_CS0 is enabled after reset. FB_CS0 is asserted
for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address
0x0000_0004 for the program counter (PC). It is assumed the reset vector loaded from address
0x0000_0004 causes the processor to start executing from external memory space decoded by FB_CS0.
9.4.3
Output Pad Strength Configuration
Output pad strength is determined during reset configuration as shown in
the output pad strength configuration can only be changed using the GPIO module. For more information,
see
Chapter 14, "General Purpose I/O Module."
9.4.4
Chip Select Configuration
The chip select (FB_CS[5:4]) configuration is selected during reset and reflected in the CCR[CSC] field.
After reset is exited, the chip select configuration cannot be changed.
9-14
Table 9-12. Serial Configuration During Reset (continued)
Override
Affected CCM
SBF_RCON Bits
Register Bit(s)
Mnemonic Bit Num
USBDIV
PLL's
PCR[OUTDIV5]
PFDR
Table 9-13. Output Pad Driver Strength Selection
Optional Pin Function Selection
Output pads configured for high drive strength
Output pads configured for low drive strength
1
Modifying the default configurations is possible only if the external
RCON pin is asserted.
MCF52277 Reference Manual, Rev. 1
9:8
00
VCO divided by 5
01
VCO divided by 6
10
VCO divided by 7
11
VCO divided by 8
7:0
Function
USB Clock Divider
PLL Multiplier
Table
9-13. After reset is exited,
1
FB_A[18]
Driven high
Driven low
Freescale Semiconductor
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