Clock Operation During Reset - Freescale Semiconductor MCF52277 Reference Manual

Input Reference/
PCR[PFDR]
Crystal Frequency
User-Defined User-Defined
SBF_RCON
User-Defined
1 (OUTDIV2 + 1) must equal 2 × (OUTDIV1 + 1).
7.3.5

Clock Operation During Reset

This section describes the PLL reset operation. Power-on reset and normal reset are described.
7.3.5.1 Power-On Reset (POR)
After VDD_PLL and the input clock are within specification, the PLL is held in reset for at least ten input
clock cycles to initialize the PLL. The reset configuration signals are used to select the multiply factor of
the PLL and the reset state of the PLL registers. While in reset, the PLL input clock is output to the device.
After RESET de-asserts, PLL output clocks generate; however, until the PSR[LOCK] bit is set, the PLL
output clock frequencies are not stable and within specification. When this bit is set, the PLL is in
frequency lock.
7.3.5.2 External Reset
When RESET asserts, the PLL input clock outputs to the device, and the PLL does not begin acquiring
lock until RESET is negated. The PSR[LOCK] bit is cleared and remains cleared while the PLL is
acquiring lock.
When running in an unlocked state, the clocks the PLL generate are not
guaranteed to be stable and may exceed the maximum specified frequency.
Freescale Semiconductor
Table 7-5. MCF52277 Clocking Scenarios (MHz) (continued)
VCO
Parallel Boot into Limp Mode
(BOOTMOD = 10 and FB_A19 = 1)
500
480
420
360
300
(BOOTMOD = 11)
500
480
420
[9:8]
360
300
MCF52277 Reference Manual, Rev. 1
OUTDIV1 ColdFire
+ 1 Core
166.67
160
3 140
120
100
Serial Boot
166.67
160
3 140
120
100
CAUTION
Internal Bus
OUTDIV5
(Core ÷ 2) 1
83.33 —
80 8
70 7
60 6
50 5
83.33 —
80 8
70 7
60 6
50 5
Clock Module
USB OTG
USB_CLKIN
60
60
60
60
USB_CLKIN
60
60
60
60
7-11