Freescale Semiconductor MCF52277 Reference Manual page 72

ColdFire Core
Opword
Extension 1
Extension 2
Core Bus
Read Data
Opword
Extension 1
Extension 2
Core Bus
Read Data
For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed
simultaneously allowing single-cycle execution. See
<ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.
3-12
Operand Execution Pipeline
DSOC
RGF
Ay
d16
Figure 3-12. V2 OEP Embedded-Load Part 1
Operand Execution Pipeline
DSOC
Rx
RGF
<mem>y
Figure 3-13. V2 OEP Embedded-Load Part 2
MCF52277 Reference Manual, Rev. 1
AGEX
<ea>y
AGEX
new Rx
Figure 3-14 where the effective address is of the form
Core Bus
Address
Core Bus
Write
Data
Core Bus
Address
Core Bus
Write
Data
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