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Address: 0xFC09_0025 (PWMCTL)
7
R
CON67
W
Reset:
0
Field
7
Concatenates PWM channels 6 and 7 to form one 16-bit PWM channel.
CON67
0 Channels 6 and 7 are separate 8-bit PWMs. There is no PWM 6 output.
1 Concatenate PWM 6 and 7. Channel 6 becomes the high order byte and channel 6 the low order byte. PWMOUT7
is the output for this 16-bit PWM signal, and PWMOUT6 is disabled. The channel 7 clock select, polarity, center align
enable, and enable bits control this concatenated output.
6
Concatenates PWM channels 4 and 5 to form one 16-bit PWM channel.
CON45
0 Channels 4 and 5 are separate 8-bit PWMs. There is no PWM 4 output.
1 Concatenate PWM 4 and 5. Channel 4 becomes the high order byte and channel 5 the low order byte. PWMOUT5
is the output for this 16-bit PWM signal, and PWMOUT4 is disabled. The channel 5 clock select, polarity, center align
enable, and enable bits control this concatenated output.
5
Concatenates PWM channels 2 and 3 to form one 16-bit PWM channel.
CON23
0 Channels 2 and 3 are separate 8-bit PWMs. There is no PWM 2 output.
1 Concatenate PWM 2 and 3. Channel 2 becomes the high order byte and channel 3 the low order byte. PWMOUT3
is the output for this 16-bit PWM signal, and PWMOUT2 is disabled. The channel 3 clock select, polarity, center align
enable, and enable bits control this concatenated output.
4
Concatenates PWM channels 0 and 1 to form one 16-bit PWM channel.
CON01
0 Channels 0 and 1 are separate 8-bit PWMs. There is no PWM 0 output.
1 Concatenate PWM 0 and 1. Channel 0 becomes the high order byte and channel 1 the low order byte. PWMOUT1
is the output for this 16-bit PWM signal, and PWMOUT0 is disabled. The channel 1 clock select, polarity, center align
enable, and enable bits control this concatenated output.
3
PWM stops in doze mode. Disables the input clock to the prescaler while in doze mode.
PSWAI
0 Allow the clock to the prescaler while in doze mode
1 Stop the input clock to the prescaler when the core is in doze mode
2
PWM counters stop in debug mode (BKPT asserted).
PFRZ
0 Allow PWM counters to continue while in debug mode
1 Disable PWM input clock to the prescaler when the core is in debug mode. Useful for emulation as it allows the
PWM function to be suspended.
1–0
Reserved, must be cleared.
24.2.7
PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is
generated with the following equation:
Any value written to this register causes the scale counter to load the new scale value (PWMSCLA).
Freescale Semiconductor
6
5
CON45
CON23
0
0
Figure 24-7. PWM Control Register (PWMCTL)
Table 24-7. PWMCTL Field Descriptions
Clock SA
=
---------------------------------------- -
×
2
MCF52277 Reference Manual, Rev. 1
4
3
CON01
PSWAI
0
0
Description
Clock A
PWMSCLA
Pulse-Width Modulation (PWM) Module
Access: User Read/Write
2
1
0
PFRZ
0
0
0
0
0
Eqn. 24-1
24-7
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