Freescale Semiconductor MCF52277 Reference Manual page 84

ColdFire Core
Table 3-9. D0 Hardware Configuration Info Field Description (continued)
Field
11 MMU present. This bit signals if the optional virtual memory management unit (MMU) is present in processor core.
MMU 0 MMU execute engine not present in core. (This is the value used for this device.)
1 MMU execute engine is present in core.
10–8 Reserved.
7–4 ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
ISA 0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (This is the value used for this device.)
Else Reserved
3–0 Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
DEBUG 0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+ (This is the value used for this device.)
1011 DEBUG_D+
Else Reserved
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
BDM: Load: 0x081 (D1)
Store: 0x181 (D1)
31 30
R CLSZ
W
Reset 0 0
15 14
R MBSZ
W
Reset
0 0
3-24
29 28 27 26
CCAS CCSZ
0 1 0 1
13 12 11 10
0 0 0 0
0 0 0
Figure 3-19. D1 Hardware Configuration Info
MCF52277 Reference Manual, Rev. 1
Description
25 24 23 22
0 0
0 1 0 0
9 8 7 6
0 0 SRAMSZ
0 0 1 0
Access: User read-only
BDM read-only
21 20 19 18
0 0 0 0
0 0 0 0
5 4 3 2
0 0
0 1 0 0
Freescale Semiconductor
17 16
0 0
0 0
1 0
0 0
0 0