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Enhanced Direct Memory Access (eDMA)
17.6.5
eDMA Set Enable Request Register (EDMA_SERQ)
The EDMA_SERQ provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQ
to enable the DMA request for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire
contents of EDMA_ERQ to be set. Reads of this register return all zeroes.
Address: 0xFC04_4018 (EDMA_SERQ)
7
R
0
W
Reset
0
Figure 17-7. eDMA Set Enable Request Register (EDMA_SERQ)
Field
7
Reserved, must be cleared.
6
Set all enable requests.
SAER
0 Set only those EDMA_ERQ bits specified in the SERQ field.
1 Set all bits in EDMA_ERQ.
5–4
Reserved, must be cleared.
3–0
Set enable request. Sets the corresponding bit in EDMA_ERQ
SERQ
17.6.6
eDMA Clear Enable Request Register (EDMA_CERQ)
The EDMA_CERQ provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQ to disable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQ to be cleared. Setting the CAER bit provides a global clear
function, forcing the entire contents of the EDMA_ERQ to be cleared, disabling all DMA request inputs.
Reads of this register return all zeroes.
Address: 0xFC04_4019 (EDMA_CERQ)
7
R
0
W
Reset
0
Figure 17-8. eDMA Clear Enable Request Register (EDMA_CERQ)
17-10
6
5
0
0
SAER
0
0
Table 17-8. EDMA_SERQ Field Descriptions
6
5
0
0
CAER
0
0
MCF52277 Reference Manual, Rev. 1
4
3
0
0
0
0
Description
4
3
0
0
0
0
Access: User write-only
2
1
0
0
SERQ
0
0
Access: User write-only
2
1
0
0
CERQ
0
0
Freescale Semiconductor
0
0
0
0
0
0
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