Freescale Semiconductor MCF52277 Reference Manual page 607

SSI_BCLK
SSI_TXD
SSI_RXD
TSCKP=1, RSCKP=1
Figure 25-34. External Gated Mode Timing - Falling Edge Clocking/Rising Edge Latching
The bit clock signals must not have timing glitches. If a single glitch occurs,
all ensuing transfers are out of synchronization.
In external gated mode, even though the transmit data line is tri-stated at the
last non-active edge of the bit clock, the round trip delay should sufficiently
take care of hold time requirements at the external receiver.
2
25.4.1.4 I S Mode
The SSI is compliant to I
June 5, 1996). Figure 25-35
Serial Clock
Frame Sync
Serial Data
Figure 25-35. I
2
I S mode can be selected by the SSI_CR[I2S] bits as follows:
2
In normal (non-I S) mode operation, no register bits are forced to any particular state internally, and the
user can program the SSI to work in any operating condition.
Freescale Semiconductor
2
S bus specification from Philips Semiconductors (February 1986, Revised
2
depicts basic I S protocol timing.
msb
Word (n-1)
Right Channel
2
S Mode Timing - Serial Clock, Frame Sync and Serial Data
Table 25-21. I
SSI_CR[I2S]
00
01
10
11
MCF52277 Reference Manual, Rev. 1
NOTE
NOTE
lsb
Word (n)
Left Channel
2
S Mode Selection
Mode
Normal mode
2
I S master mode
2
I S slave mode
Normal mode
Synchronous Serial Interface (SSI)
msb
Word (n+1)
Right Channel
25-39