Freescale Semiconductor MCF52277 Reference Manual page 257

service routine with the controller level masking functionality enabled. The time scale in this diagram is
not meant to be accurate.
Interrupt
Request
Core
Activity
SR[I]
0xF
CLMASK
SLMASK
Interrupts
Enabled
Note: Not to scale
Consider the events depicted in each segment (A–F) of the above diagram.
In A, an interrupt request is asserted, which is then signalled to the core.
As B begins, the interrupt request is recognized, and the core begins interrupt exception processing. During
the core's exception processing, the IACK cycle performs and the interrupt controller returns the
appropriate vector number. As the interrupt acknowledge read performs, the vector number returns to the
core. The contents of the CLMASK register load into the SLMASK register, and the CLMASK register
updates to the level of the acknowledge interrupt. Additionally, the processor raises the interrupt mask in
the status register (SR[I]) to match the level of the acknowledged request. At the end of the core's
exception processing, control passes to the interrupt service routine (ISR), shown as the beginning of
segment C.
During C, the initial portion of the ISR executes. Near the end of this segment, the ISR accesses the
peripheral to negate the interrupt request source. At the conclusion of segment C, the SR[I] field can be
lowered to re-enable interrupts with a priority greater than the original request.
The bulk of the interrupt service routine executes in segment D, with interrupts enabled. Near the end of
the service routine, the SR[I] field is again raised to the original acknowledged level, preparing to perform
the context switch.
At the end of segment E, the original value in the saved level mask (SLMASK) is restored in the current
level mask (CLMASK). Optionally, the service routine can directly load the CLMASK register with any
value with pending interrupt requests of certain levels need to be examined.
In segment F, the interrupt service routine completes execution. During this period of time, it is possible
to access the interrupt controller with a software IACK to see if there are any pending properly-enabled
requests. Checking for any pending interrupt requests at this time provides ability to initiate processing of
Freescale Semiconductor
A B
iack
Figure 15-14. Interrupt Service Routine and Masking
MCF52277 Reference Manual, Rev. 1
C D
Interrupt Service Routine
n
n
0xF
≤ n Disabled
Interrupt Controller Modules
E F
swiack
n
0xF
15-19