Freescale Semiconductor MCF52277 Reference Manual page 122

Cache
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of
non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction
fetch is processed, as defined by
references can hit in the buffer, but the data is never loaded into the memory array.
Table 5-7 shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch.
CACR
[CENB]
0
0
1
1
1
5-10
Table 5-7. For this condition, the line-fill buffer is loaded and subsequent
Table 5-7. Instruction Cache Operation as Defined by CACR
CACR Type of
[CEIB] Instruction Fetch
0 N/A
1 N/A
X Cacheable
0 Non-cacheable
1 Non-cacheable
MCF52277 Reference Manual, Rev. 1
Description
Cache is completely disabled; all instruction fetches
are word or longword in size.
All instruction fetches are word or longword in size
Fetch size is defined by Table 5-6
line-fill buffer can be written into the memory array
All instruction fetches are word or longword in size,
and not loaded into the line-fill buffer
Instruction fetch size is defined by
loaded into the line-fill buffer, but are never written into
the memory array.
and contents of the
Table 5-6 and
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