Serial Clock (Dspi_Sck) - Freescale Semiconductor MCF52277 Reference Manual

29.2.6

Serial Clock (DSPI_SCK)

DSPI_SCK is a serial communication clock signal. In master mode, DSPI generates DSPI_SCK. In slave
mode, DSPI_SCK is an input from an external bus master.
29.3 Memory Map/Register Definition
Table 29-2 shows the DSPI memory map.
Address
0xFC05_C000 Module Configuration Register (DSPI_MCR)
0xFC05_C008 DSPI Transfer Count Register (DSPI_TCR)
0xFC05_C00C DSPI Clock and Transfer Attributes Register (DSPI_CTARn),
+ (n × 0x04)
n=0:7
0xFC05_C02C DSPI Status Register (DSPI_SR)
0xFC05_C030 DSPI DMA/Interrupt Request Select and Enable Register
(DSPI_RSER)
0xFC05_C034 DSPI Push TX FIFO Register (DSPI_PUSHR)
0xFC05_C038 DSPI Pop RX FIFO Register (DSPI_POPR)
0xFC05_C03C DSPI Transmit FIFO Register n (DSPI_TXFRn),
+ (n × 0x04)
n=0:15
0xFC05_C07C DSPI Receive FIFO Register n (DSPI_RXFRn),
+ (n × 0x04)
n=0:15
29.3.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits that configure various attributes associated with DSPI operation. The HALT
and MDIS bits can be changed at any time, but only take effect on the next frame boundary. Only the
HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is running.
The DSPI_MCR[MDIS] bit is set at reset.
Freescale Semiconductor
Table 29-2. DSPI Module Memory Map
Register
NOTE
MCF52277 Reference Manual, Rev. 1
DMA Serial Peripheral Interface (DSPI)
Width Access Reset Value
32 R/W 0x0000_4001
32 R/W 0x0000_0000
32 R/W 0x7800_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R 0x0000_0000
32 R 0x0000_0000
32 R 0x0000_0000
Section/Page
29.3.1/29-5
29.3.2/29-8
29.3.3/29-8
29.3.4/29-13
29.3.5/29-15
29.3.6/29-16
29.3.7/29-18
29.3.8/29-18
29.3.9/29-19
29-5