Freescale Semiconductor MCF52277 Reference Manual page 585

Field
12 Transmit data register empty 0. Similar description as TE1 but pertains to Tx FIFO 0 and it is not necessary to be
TDE0 in two-channel mode for this bit to be set.
0 Data available for transmission
1 Data needs to be written by the core for transmission
11 Receiver overrun error 1. Only valid in two-channel mode. Indicates an overrun error has occurred.
ROE1
Rx FIFO1
Enabled
Disabled
Rx FIFO1
Enabled
Disabled
Note: If Rx FIFO 1 is enabled, the RFF1 flag indiates the FIFO is full.
If Rx FIFO 1 is disabled, the RDR1 flag indicates the SSI_RX1 register is full.
10 Receiver overrun error 0. Similar description as ROE1 but pertains to Rx FIFO 0 and it is not necessary to be in
ROE0 two-channel mode for this bit to be set.
0 No overrun detected
1 Receiver 0 overrun error occurred
9 Transmitter underrun error 1. Only valid in two-channel mode. When a transmit underrun error occurs, the
TUE1 previous data is retransmitted. In network mode, each time slot requires data transmission (unless masked
through the SSI_TMASK register), when the transmitter is enabled.
Tx FIFO1
Enabled
Disabled
Tx FIFO1
Enabled
Disabled
Freescale Semiconductor
Table 25-8. SSI_ISR Field Descriptions (continued)
Receiver overrun error 1 interrupt
Required conditions
• SSI_IER[RIE] set
• SSI_IER[ROE1] set
ROE1 is set when
all of the following occur
• RXSR is full
• Rx FIFO1 is full
• RXSR is full
• SSI_RX1 is full
Transmit underrun error 1 interrupt
Required conditions
• SSI_IER[TIE] set
• SSI_IER[TUE1] set
TUE1 is set when
all of the following occur
• TXSR is empty
• SSI_ISR[TDE1] set
• Transmit time slot occurs
MCF52277 Reference Manual, Rev. 1
Description
• SSI_ISR[ROE1] sets
ROE1 is cleared when
any of the following occur
• Reading SSI_ISR when ROE1 is
set
• SSI reset
• POR reset
• SSI_ISR[TUE1] sets
TUE1 is cleared when
any of the following occur
• Reading SSI_ISR when TUE1 is
set
• SSI reset
• POR reset
Synchronous Serial Interface (SSI)
Trigger
Trigger
25-17