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Liquid Crystal Display Controller (LCDC)
Field
31–5
Reserved, must be cleared.
4–0
Panning offset. Defines the number of bits that the data from memory is panned to the left before processing. The
POS
POS field is read by the LCDC once at the beginning of each frame.
For example, in 4 bpp mode, setting POS = 16 shifts the data 16bits, which equates to panning the image by 4 pixels
to the left.
Note: Use the LSSAR register to shift the data more than 32 bits or for 18 bpp panning.
To achieve panning of the final image by N bits:
21.3.11 LCDC Sharp Configuration Register (LCD_SCR)
For 2 bpp modes, full black and full white are the two predefined display levels. The other two
intermediate gray-scale shading densities can be adjusted within the Sharp configuration register. The
LCD_SCR register also controls the relative delay timing of the LCD_CLS, LCD_REV, and LCD_PS
signals. For detailed Sharp panel settings, please refer to panel's data sheet. The TFT timing diagram that
shows the relationship between these signals is shown in
Address: 0xFC0A_C028 (LCD_SCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
PS_RISE_DELAY
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1
Field
31–26
LCD_PS rise delay. Controls the delay of the rising edge of LCD_PS relative to the falling edge of LCD_CLS.
PS_RISE_
Total delay time is equal to PS_RISE_DELAY LCD_LSCLK periods.
DELAY
0x00 Zero LCD_LSCLK periods
...
0x3F 63 LCD_LSCLK periods
25–24
Reserved, must be cleared.
21-14
Table 21-13. LCD_POR Field Descriptions
Bits Per Pixel
1
2
4
8
12/16
0 0
CLS_RISE_DELAY
Figure 21-12. LCD Sharp Configuration Register (LCD_SCR)
Table 21-14. LCD_SCR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Description
Effective # of pixels
POS
Panned on Image
N
N
2N
N
4N
N
8N
N
16N
N
Figure
21-13.
0 0 0 0
REV_TOG
GLE_DELAY
Description
Access: User read/write
9
8
7
6
5
4
3
2
1
GRAY2
GRAY1
Freescale Semiconductor
0
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