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Chapter 18
FlexBus
18.1
Introduction
This chapter describes external bus data transfer operations and error conditions. It describes transfers
initiated by the ColdFire processor and includes detailed timing diagrams showing the interaction of
signals in supported bus operations.
In this chapter, unless otherwise noted, clock refers to the FB_CLK used for
the external bus (f
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode, the data
bus is switched dynamically between the SDRAM controller and the
FlexBus module. However, when the SDRAM controller is in DDR mode,
D[31:16] is dedicated to the SDRAM data bus and D[15:0] is dedicated to
the FlexBus data bus. In this case, external pins D[15:0], are mapped
internally to the upper two bytes of the FlexBus data bus, FB_D[31:16].
This chapter only uses FB_D[31:0] or FB_D[31:X] to designate the data
bus, but the actual pins used depend on the setting. Take this into
consideration throughout this chapter.
18.1.1
Overview
A multi-function external bus interface called the FlexBus interface controller is provided on the device
with basic functionality of interfacing to slave-only devices with a maximum bus frequency up to
83.33 MHz. It can be directly connected to the following asynchronous or synchronous devices with little
or no additional circuitry:
•
External boot ROMs
•
Flash memories
•
Gate-array logic
•
Other simple target (slave) devices
For asynchronous devices, a simple chip-select based interface can be used.
The FlexBus interface has up to six general purpose chip-selects, FB_CS[5:0]. (The actual number of chip
selects available depends upon the pin configuration. See
can be dedicated to boot ROM access and programmed to be byte (8 bits), word (16 bits), or longword
(32 bits) wide. Control signal timing is compatible with common ROM and flash memories.
Freescale Semiconductor
NOTE
).
sys/2
MCF52277 Reference Manual, Rev. 1
Table 2-2
for more details.) Chip-select FB_CS0
18-1
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